1. Field of the Invention
This invention relates to processes for forming C4 solder bumps and more particularly to the metallurgy employed for enhanced characteristics of the joints.
2. Description of Related Art
Controlled Collapse Chip Connection (C4) solder ball, flip chip connections have been used for more than thirty years to provide flip chip interconnections between semiconductor devices and substrates. Cylindrical C4 solder bumps are formed above an insulation layer and above the exposed surfaces of connector pads each of which is exposed through a VIA hole in the insulation layers. Later the C4 solder bumps are heated above the melting point until the C4 solder bumps reflow by controlled collapse to form C4 solder balls. The actual C4 solder bumps may be fabricated using a number of different processing techniques, including evaporation, screening, and electroplating. Fabrication by electroplating requires a series of basic steps which typically include but are not limited to the deposition of a metallic seed layer on the top surface of the wafer final passivation layer, the application of an imaged photoresist (in the pattern of C4 solder bumps), the electrodeposition of solder, the stripping of the photoresist, and the subetching of the metallic seed layer to isolate the C4 bumps. The metallurgy which is chosen for the seed layer is crucial to both the fabrication process and the ultimate C4 structure.
The first fundamental operation in forming C4 solder bumps by electrolytic means is to deposit a continuous stack of metal films across the wafer to be bumped. The so-called xe2x80x9cconductive metalxe2x80x9d performs a dual function. First, it provides a conductive path for current flow during the electrolytic deposition of the C4 solder bumps. Second, the conductive metal remains under the C4 solder bumps and forms the basis for the Ball Limiting Metallurgy (BLM) underneath the C4 solder balls, which ultimately defines the field reliability of the device. Therefore, the BLM layers must include at least one layer that is conductive enough to permit uniform electrodeposition across the entire expanse of the wafer. The bottom layer must adhere well to the underlying passivation, and the top layer must interact sufficiently with the solder to form a reliable bond. In addition, the BLM may contain barrier layers which prevent the solder from detrimentally interacting with the underlying device constituents. Finally, the stresses generated by the composite seed layer stack should be low enough to sustain the reliability of C4 solder ball joints when exposed to various thermo-mechanical stresses. As a result, both the constituents and the thicknesses of the various BLM layers (i.e. barrier layer and seed layer metals) are carefully chosen to provide sufficient functionality under a wide variety of thermal, mechanical and environmental conditions.
Because of its relatively high conductivity, copper (Cu) is used frequently as an electroplating conductive metal. This method has proven successful for C4 solder bump applications, when including a layer of copper in the seed layer stack greater than 1000 Angstroms in thickness), provides adequate conductivity to electroplate C4 solder bumps uniformly across an entire 300 mm diameter wafer. In many cases, particularly those in which the C4 solder bumps contain a high percentage of lead (Pb) metal (greater than 90% Pb), the presence of copper in the BLM metal layers also satisfies the other objectives listed above. Upon heat treatment, lead-rich C4 solder bumps containing small amounts of tin beneficially react with the copper layer to form stable copper tin (Cuxe2x80x94Sn) intermetallic compounds that remain intact over a wide range of field conditions.
However, there are more recent applications in which it can actually be detrimental to include copper as a BLM constituent of the seed layer. Many semiconductor packages now utilize organic carriers, which cannot tolerate temperatures in excess of 240xc2x0 C. In addition, many high performance semiconductor devices are now being designed with low K dielectric materials that become unstable at temperatures above 300xc2x0 C. Finally, there is a strong market demand for lead-free solders, which are gradually being introduced as high-Sn composites. For these reasons, high-lead solder bumps that melt at temperatures greater than 300xc2x0 C. are not universally applicable. As a result, C4 solder bumps which contain higher percentages of tin and melt at temperatures less than 220xc2x0 C. are becoming industry standard.
High-Sn C4""s are easily fabricated by electrodeposition, provided that a sufficiently conductive seed layer such as copper is employed. Unfortunately, the presence of copper in the final BLM structure does not necessarily produce a reliable structure. Upon heat treatment, copper reacts so aggressively in the presence of Sn-rich solder bumps that a BLM structure containing copper becomes unstable and deteriorates rapidly. One way to mitigate this effect is to utilize copper as a conductor, but protect it with a less reactive barrier layer, such as Ni. This solution does minimize exposure to BLM attack, but under extreme field conditions, the high-Sn solder has the potential to eventually attack the copper portion of the BLM from the periphery of the C4 solder balls. Completely removing copper from the seed layer is plausible, but renders it extremely difficult to electroplate C4 solder balls uniformly without a sufficiently conductive seed layer.
FIGS. 1A and 1B illustrate a prior art process for manufacturing one or more C4 solder bump(s) 24 and forming one or more C4 solder balls 30 therefrom on a conformal, seed layer stack 15 formed above a metal contact 11 formed on a semiconductor device 10. The seed layer stack 15 is composed of a base of at least one metal adhesion layer 16. As shown in FIGS. 1A and 1B the device 10 includes a base of two metal layers 16/20. To complete the seed layer stack, the metallic base layers 16/20 are covered by a conductive metal (CM) layer 22, that is composed of copper (Cu). A portion of the semiconductor device 10 is shown to illustrate an example of a C4 bumping process sequence in which the seed layer stack 15 is used during processing. As will be explained below, after processing only a portion of the copper originally included in CM layer 22 remains in CM layer 22N as a part of the seed layer stack 15 of layers 16N, 20N and 22N in FIG. 1B.
The device 10 on which the seed layer stack 15 and the C4 solder bump 24 are formed includes a lower insulator layer 12 in which the metal contact 11 has been formed. The metal contact 11 is partially covered by a second insulator layer 14 through which a tapered VIA hole has been formed exposing a portion of the top surface of the metal contact 11. The seed layer stack 15 is formed on the surfaces of the second insulator layer 14 and the exposed portion of the top surface of the metal contact 11. The C4 solder bump 24 is formed over the seed layer stack 15 in an opening formed in a photoresist mask PRxe2x80x2.
The series of process steps used to fabricate structures in FIGS. 1A and lB begins with a partially formed device 10 which includes the planar contact 11 and the lower insulation layer 12, which have been formed on the surface a substrate 9, such as a silicon wafer (as shown) or a dielectric layer formed thereabove, as will be well understood by those skilled in the art. The contact and the lower insulation layer 12 are shown as having upper surfaces which are formed in a single plane. An upper insulation layer 14 is formed covering both a portion of the planar contact 11 and the lower insulation layer 12 with a tapered VIA hole opening through the upper insulation layer 14 exposing a portion of the top surface of the contact 11.
The processing sequence is as follows:
1. Deposit a multi-layer, conformal, seed layer stack 15 on the surface of insulator 14 and the exposed surface of metal contact layer 11. The seed layer stack 15 includes a conformal, lower metal (M1) adhesion layer 16 covering the upper dielectric layer and reaching down through the VIA hole to contact the portion of the top surface of contact 11 exposed by the VIA hole. A conformal, intermediate metal (M2) layer 20 is formed over the adhesion layer 16 which is covered, in turn, with a conformal conductive metal (CM) layer 22 on the surface of M2 layer 20 which is composed of a conductive metal, e.g. copper (Cu).
2. Deposit a thick-film of photoresist PR on top of the CM layer 22 of stack 15.
3. Expose and develop the photoresist PR to form a photoresist mask PRxe2x80x2 forming the C4 solder bump images in the photoresist mask PRxe2x80x2 defining the locations of the C4 solder bumps to be formed into the C4 solder balls 30 of FIG. 1B.
4. Electroplate the C4 solder bumps 24 which are usually high in lead (Pb) content.
5. Remove the photoresist mask PRxe2x80x2 by chemical dissolution.
6. Remove the exposed, peripheral portions of the seed layer stack 15 including peripheral portions of the CM layer 22, the M2 layer 20 and M1 layer 16, aside from the C4 solder bumps 24 to form BLM pads 15N (shown in FIG. 1B) for shaping of the solder bump 26 into the solder ball 30 during the reflow step.
In other words in an array of C4 solder bumps 24, the peripheral portions of the seed layer stack 15 are removed from the surface of the insulator 14 between C4 solder bumps 24, by metal etching techniques leaving the narrowed layers 22N, 20N, and 16N of BLM pad 15N which are centered under the C4 solder bump 24.
7. Reflow the C4 solder bump(s) 24 to form the C4 solder ball(s) 30 shown in FIG. 1B on top of the surface copper/intermetallic CM layer 22N of the BLM pads 15N.
FIG. 1A illustrates the fully deposited device 10 prior to the removal of the photoresist mask PRxe2x80x2 and the superfluous, peripheral portions of the CM layer 22 composed of copper (Cu), the M2 layer 20, and the M1 layer 16 aside from the C4 solder bump 24.
FIG. 1B depicts the final device 10 after the removal of the photoresist mask PRxe2x80x2, removal of the peripheral portion of seed layer stack 15 leaving a narrower BLM pad 15N, and reflowing of the C4 solder bump 24 to form the C4 solder ball 30. Note that the removal of the peripheral portion of the seed layer stack 15 forms the narrower BLM pad 15N composed of copper CM layer 22N, M2 metal layer 20N and M1 metal adhesion layer 16N. In this traditional embodiment, the original underlying copper CM layer 22, between the reflowed C4 solder ball 30 and the intermediate M2 metal layer 20N, has been transformed into an acceptable BLM copper/tin intermetallic layer 22N (that includes both converted and unconverted copper) which remains as an integral part of the structure of the final BLM stack 15N, which produces highly reliable interconnects when the weight percentage of tin (Sn) remains low, i.e. less than ten percent ( less than 10%) in the lead/tin C4 solder bump 24.
FIGS. 2A and 2B show the two steps illustrated by FIGS. 1A and 1B after substitution of a tin enriched C4 solder bump 26 containing high-tin (high-Sn) tin-lead solders, such as tin-lead (SnPb) eutectic (63% Sn/37% Pb) into the method of FIGS. 1A and 1B, which yields less robust interconnects. FIG. 2B depicts the final device 10 after the removal of the photoresist mask PRxe2x80x2, which was followed by removal of the peripheral portion of the seed layer stack 15 and finally reflowing of the C4 solder bump 26 to form the C4 solder ball 30B. As in FIG. 1B, in FIG. 2B peripheral portions of the seed layer stack 15 have been removed therefrom to form BLM pads 15B for shaping of the solder bump 26 into the solder ball 30 during the reflow step. However in this case the ultimate result is that a shorter BLM pad 15B is formed during the sequence of steps in the process. As shown in FIG. 2B, the BLM pad 15B is composed of only the intermediate M2 layer 20B and the lower M1 layer 16B. The sharp difference is that in this case there is no remaining trace of the CM layer 22 on top of final BLM pad 15B. The copper in the CM layer 22 was consumed during the reflow process which formed the C4 solder ball 30B because of the presence of large amounts of tin (Sn). During the reflow process, the interaction between the copper and the tin at the interface between the C4 solder bump 26 and the CM layer 22 initially causes deterioration of the CM layer 22 as the copper is consumed when combining with the tin. Ultimately, the result is the consumption and the migration of the remainder of the copper in the CM layer 22 to form copper tin (CuSn) intermetallics 221 in the C4 solder ball 30B during completion of the process of formation thereof. This process eventually leads to voiding, i.e. formation of voids 22V, and the result is a highly resistive interface between the M2 layer 20B and the bulk of the C4 solder ball 30B.
In summary, in FIG. 2B the CM layer 22 of FIG. 2A which was composed of copper is absent because it has been completely absorbed in the C4 solder ball 30B leaving copper/tin (CuSn) intermetallic regions 221 and voids 22V which are located in the region of the C4 solder ball 30B between the intermetallic regions 221 and the intermediate M2 layer 20B producing the undesirable result of a highly resistive interface between the intermediate M2 layer 20B and the C4 solder ball 30B.
Commonly assigned U.S. Pat. No. 5,937,320 of Andricacos et al. for xe2x80x9cBarrier Layers for Electroplated SnPb Electric Solder Jointsxe2x80x9d describes fabricating a C4 flip-chip structure with three BLM layers capped by an additional BLM barrier layer interfacing between the electroplated tin-rich C4 solder bump and a copper layer. The barrier layer is provided to protect the conductive metal layer (copper) from attack by the tin (Sn) in the lead-tin solder which is used to form the solder ball. The barrier layer is composed of nickel, iron, cobalt or alloys thereof. The preferred barrier layer is nickel which is electroplated through the same photoresist mask as the solder. The Andricacos et al. process requires an additional electroplating step to add the barrier layer which separates the copper from the tin-rich C4 solder bump. Changing plating baths adds complexity and an additional step in the bump plating process and requires intermediate steps of plating the barrier layer onto the workpiece for a timed interval, removal of the workpiece from the barrier layer bath, rinsing the workpiece and reinsertion of the workpiece into a C4 solder bump plating bath. Moreover, the resulting C4 bump is formed on an additional barrier layer above the other barrier layers. The thickness of the barrier layer adds a fourth layer on top of the three BLM layers with additional electrical resistance added to the layers providing the connection between the C4 solder ball and the contact below the various barrier layers.
U.S. Pat. No. 5,885,891 of Miyata et al for xe2x80x9cMethod of Manufacturing Semiconductor Devicexe2x80x9d provides a single BLM layer during the process of electroplating the solder bump composed of a thin layer of titanium which has been oxidized aside from a mask formed where the bump is to be formed. Then the mask is removed and the bump is plated without any photoresist onto the titanium which has been exposed by removal of the mask. The titanium is used as the cathode in an electroplating process. A problem with this procedure is that the titanium is a poor conductor and for a large device the current/resistance (IR) voltage drop will result in excessive variations in the thickness of the solder balls plated in the electroplating bath. The fact that the photoresist is absent results in a different geometry of C4 solder bump in the form of a mushroom with the disadvantage that mushrooms can cause formation of short circuits on reflow (melting). Also, mushrooming makes it difficult to control dimensional and compositional uniformity.
For background information, see German Offenlegunschrift DE 197 16 044 A 1 and Japan Patent Number 3-137186.
The present invention comprises a method for using a highly conductive metal layer such copper (Cu), gold (Au), silver (Ag) or platinum (Pt) as the key conductive component of the seed layers, but selectively removing it so it does not end up in the final structure.
The process of this invention can be implemented with one or more barrier layers to optimize C4 reliability.
In accordance with this invention, a method is provided for forming a solder structure on a substrate starting with contacts exposed through an insulating layer and forming a base over the contacts, with the base having a top surface and being composed of at least one metal layer. Form a conductive metal (CM) layer, with an upper surface, over the base. Form a mask over the top surface of the (CM) layer, with the mask having C4 solder bump openings therethrough in the shape of C4 solder bump images down to expose the CM layer above the contacts. Etch away the exposed portions of the CM layer below the C4 solder bump openings forming through holes, with sidewalls, on the CM layer down to the top surface of the base, thereby forming C4 solder bump plating sites on the top surface of the base, with the CM layer remaining intact aside from the through holes. Deposit solder over the base to form C4 solder bumps to fill the C4 solder bump plating sites in the C4 solder bump openings and through the sidewalls thereof plating solder into the solder bump openings. Remove the mask and etch away the remainder of the CM layer. Then etch away the base aside from the C4 solder bumps thereby forming BLM pads which are plated with the C4 solder bumps. Preferably, form the C4 solder bumps into C4 solder balls above the BLM pads, form an intermediate metal layer above the one metal layer before forming the CM layer, form an intermediate metal layer above the one metal layer before forming the CM layer, and reflow the C4 solder bumps to form C4 solder balls over the BLM pads. Preferably, perform the step of filling the C4 solder bump openings with a barrier layer over the base, after etching away the exposed portions of the CM layer below the C4 solder bump openings and before electroplating solder over the base to form C4 solder bumps. Preferably, deposit the C4 solder bumps by providing an electroplating current through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings with the C4 solder bumps being in contact with the CM layer on the periphery of the through holes by providing an electroplating current passing through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings. Preferably, form the CM layer with at least one of the metals selected from the group consisting of Cu, Au, Ag, and Pt; and form an intermediate layer of metal above the one metal layer before forming the CM layer.
In accordance with another aspect of this invention, form a solder ball on a substrate starting with contacts exposed through an insulating layer and forming a base over the contacts, with the base having a top surface and is composed of at least one metal layer. Form a CM layer with an upper surface over the base. Form a mask over the top surface of the CM layer with C4 solder bump openings therethrough in the form of windows in the shape of C4 solder bump images down to the surface of the CM layer above the contacts. Etch away the exposed portions of the CM layer below the C4 solder bump openings, thereby forming through holes, with sidewalls, in the CM layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the CM layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. Plate solder onto the top surface of the base at the C4 solder bump plating sites filling the C4 solder bump openings by providing an electroplating current through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings with the C4 solder bumps is in contact with the CM layer on the periphery of the through holes by providing an electroplating current passing through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings. Deposit solder over the base to form C4 solder bumps filling the C4 solder bump plating sites within the C4 solder bump openings and through the sidewalls thereof to plate the solder in the solder bump openings. Remove the mask. Then etch away the base aside from the C4 solder bumps thereby forming BLM pads which are plated with the C4 solder bumps. Preferably, reflow the C4 solder bumps to form a solder balls therefrom over the remaining base regions after the step of etching away the base aside from the C4 solder bumps leaving remaining base regions self-aligned with the C4 solder bumps; form another metal layer above the adhesion metal layer before forming the CM layer, form an intermediate layer above the adhesion metal layer before forming the CM layer, and reflow the C4 solder bumps to form a solder balls over the BLM pads. Preferably, the method includes depositing solder to form C4 solder bumps on the top surface of the base at the C4 solder bump plating sites filling the C4 solder bump openings by providing an electroplating current through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings with the C4 solder bumps is in contact with the CM layer on the periphery of the through holes by providing an electroplating current passing through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings. Preferably, the CM layer is formed by at least one of the metals selected from the group consisting of Cu, Au, Ag, and Pt.
In accordance with still another aspect of this invention, a method of forming a solder ball on a substrate starts with contacts exposed through an insulating layer and forming a base over the contacts, with the base having a top surface and is composed of at least one metal layer. Form a CM layer with a upper surface over the base. Form a mask over the top surface of the CM layer with C4 solder bump openings therethrough in the form of windows in the shape of C4 solder bump images down to the surface of the CM layer above the contacts. Etch away the exposed portions of the CM layer below the C4 solder bump openings, thereby forming through holes, with sidewalls, in the CM layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the CM layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. Deposit a barrier layer with a barrier surface over the top surface of the base. Plate solder onto he barrier surface at the C4 solder bump plating sites filling the C4 solder bump openings by providing an electroplating current through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings with the C4 solder bumps is in contact with the CM layer on the periphery of the through holes by providing an electroplating current passing through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings. Deposit solder over the base to form C4 solder bumps filling the C4 solder bump plating sites within the C4 solder bump openings and through the sidewalls thereof to plate the solder in the solder bump openings. Remove the mask. Then etch away the base aside from the C4 solder bumps thereby forming Ball Limiting Metallurgy (BLM) pads on which C4 solder bumps have been formed. Preferably, form the C4 solder bumps into C4 solder balls above the BLM pads. Preferably, the CM layer is formed by at least one of the metals selected from the group consisting of Cu, Au, Ag, and Pt, the adhesion layer is composed of a material selected from the group consisting of tungsten and titanium/tungsten (TiW), the intermediate layer is composed of CrCu, and the barrier layer is composed of a material selected from the group consisting of Ni, NiFe alloy, NiP alloy, Co, and CoP alloy. Preferably, include the step of depositing solder to form C4 solder bumps on the barrier surface of the barrier layer filling the C4 solder bump openings by providing an electroplating current through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings with the C4 solder bumps is in contact with the CM layer on the periphery of the through holes by providing an electroplating current passing through the CM layer and through the sidewalls thereof to plate the solder in the solder bump openings.